Field
The described embodiments relate to computing devices. More specifically, the described embodiments relate to a technique for fast entry into a power-gated state.
Related Art
Many computer systems employ power-saving techniques to reduce power consumption. Reducing power consumption is particularly important in portable electronic devices, where smaller power consumption generally translates to longer battery life, which in turn translates to increased productivity and end-user satisfaction.
One technique used for power saving is power-gating. In computer systems that employ power gating, when operating in a power-gated mode, the voltage to some circuits, e.g., the voltage to a processor, is reduced to a level below the normal operating voltage for those circuits. Because the power consumption of a circuit is proportional to the voltage applied to the circuit, reducing the voltage to some circuits can reduce the power consumption of the computer system.
A downside of reducing the voltage to a circuit is that the state of the circuit can be lost. For example, when the voltage supplied to a processor is reduced, the architectural state of the processor (e.g., register values and/or internal memory contents) can be lost. Some designs counteract such memory loss by saving the entire architectural state to temporary storage during entry into the power-gated mode, and then restoring the architectural state from the temporary storage when exiting the power-gated mode and returning to normal operation. However, saving the entire architectural state prior to entering the power-gated mode can be time consuming, which can increase the time required to enter the power-gated mode and/or reduce how frequently the processor can enter the power-gated mode.
Another technique for power-gating is to support retention mode in circuits in the computer system. For this technique, a circuit does not lose its architectural state in the low-power mode. Instead, the circuit enters a special mode called retention mode where the contents are preserved. Compared to a pure power-gating solution, this technique has a faster exit time from the low-power mode. However, there are two disadvantages to this technique. First, because the contents need to be preserved in the retention mode, the operating voltage for the circuit typically cannot be reduced as drastically as with the above described power-gating solution. This reduces the amount of power savings. Second, the system design cost increases significantly to support retention mode compared a non-retention mode.
Throughout the figures and the description, like reference numerals refer to the same figure elements.